Formalizing the gap between what hardware guarantees architecturally and what microarchitectural implementations expose as observable side effects. Fulbright Scholar · M.Sc. ELTE Budapest · Available Phoenix, AZ from August 2026 · Open to relocation.
I work at the intersection of formal methods, compiler infrastructure, and microarchitectural security. My research asks one question from multiple angles: what does hardware expose to software that the abstraction layer promises will not be observable - and how do we formally characterize, verify, and close that gap?
My M.Sc. thesis formalized trust-boundary information leakage as a confidentiality invariant violation over compiler-visible ABI semantics - syntactically correct, UB-free programs that violate system-level security guarantees through object representation and padding behavior. The formal machinery maps directly to Caroline Trippel's hardware-software security contracts framework, just instantiated at the compiler layer rather than the hardware layer.
My current research, ISA-Silent Channels, extends this to the ISA boundary. The RISC-V formal specification defines what instructions do architecturally. It says nothing about what microarchitectural state - cache timing, branch predictor history, TLB effects - becomes observable as a side effect. I am formalizing that gap and demonstrating it with cache-timing tooling, targeting a HASP workshop paper.
Before research: six years as an Information Systems Security Officer in the Air National Guard (TS/SCI), including TEMPEST enforcement and COMSEC/KMI management. ASU Summa Cum Laude, GPA 3.81. CLS Russian. PhD applicant targeting 2027.
The RISC-V ISA formal specification defines what instructions do architecturally. It says nothing about what microarchitectural state becomes observable as a timing side effect. Two architecturally equivalent instruction sequences can be microarchitecturally distinguishable through cache timing - yet the ISA formal model has no predicate capturing this distinction. That gap is where every Spectre-class attack lives.
Formalized trust-boundary information leakage as a confidentiality invariant violation over compiler-visible ABI semantics. Programs can be syntactically correct, undefined-behavior free, and still violate system-level security invariants through object representation and padding behavior - a semantic class the type system cannot enforce.
Bootloader-stage mechanism to selectively disable hardware devices in the Linux device tree on a secure mobile platform, reducing attack surface before userspace initialization. A hardware-software boundary security problem: enforcing a source-level security policy across cross-compilation toolchains, U-Boot, and embedded Linux internals.
Competitive federal fellowship funding graduate research abroad. Selected to conduct M.Sc. research at Eotvos Lorand University (ELTE) Budapest, one of Central Europe's leading research universities. Fulbright is the U.S. government's flagship international exchange program.
Highly competitive language immersion award granted to fewer than 550 Americans annually across all languages. Selected for Russian based on demonstrated academic merit and national security relevance.
Graduated with highest academic distinction. GPA 3.81 / 4.00.
Formalizing microarchitectural observability gaps in the RISC-V ISA specification and demonstrating them with cache-timing tooling. Formal characterization of where the ISA Sail model is silent about observable side effects - the structural property underlying Spectre-class attacks. Targeting a HASP workshop paper.
Built a formal model of trust-boundary information leakage grounded in C/C++ object representation semantics and ABI layout behavior. Implemented a complete Clang-Tidy static analysis module with CodeChecker integration, evaluated on open-source C libraries with manual validation of all emitted diagnostics. Zero false positives in real-world findings.
Built a bootloader-stage device-tree hardening mechanism for a secure mobile platform, reducing hardware attack surface before userspace initialization. Worked across cross-compilation toolchains, U-Boot, and embedded Linux internals - direct exposure to the semantic gap between source-level security policy and deployed binary behavior on real hardware.
Six years executing security authorization and compliance for mission-critical operational systems. NIST 800-53 controls, ATO packages, POA&M management, and incident coordination. TEMPEST enforcement per AFMANs - controlling electromagnetic emanation risks from hardware systems. COMSEC management including KMI operations and cryptographic material accountability. Separated as Senior Airman; TS/SCI voluntarily relinquished Aug 2024 (reinstatement eligible).
I'm actively looking for hardware security research and compiler security engineering
roles starting August 2026 - in Phoenix, remote, or Bay Area. Particularly interested
in positions at the hardware-software security boundary: formal verification, microarchitectural
security research, compiler security, or hardware security architecture.
If you're working on problems at the intersection of formal methods, compiler infrastructure,
and hardware security - I'd genuinely love to talk.